IR3519 page 1 of 10 www.irf.com 8/15/08 synchronous mosfet gate driver ic features ? 7v/2a gate drivers (5a gatel sink current) ? 15ns adaptive non-overlap control ? integrated boot-strap synchronous pfet ? supports 3.3v and 5v pwm input signals ? tri-state pwm input fo r power stage shutdown ? sub 50ns minimum pulse width supports 2mhz per- phase operation ? dual function en/uv pin provides enable input and power good output ? small thermally enhanced 8l son & 3 x 3mm mlpd packages ? rohs compliant description the IR3519 is extended voltage range high-speed gate driver optimized for switching power supply applications. performance is achieved by 7v/2a gate source and 5-a sink drive capability and is capable of operating at frequencies of up to 2mhz. the 0.4- impedance of the lower gate driver holds the gate of the synchronous mosfet below its threshold to prevent shoot-through current during high dv/dt phase node transitions. the IR3519 includes a two-way enable/under voltage power good signal. systems without 3-state featured controllers can use the en/uv input/output to hold both outputs low during conv erter shut down. application circuit order information device package order quantity IR3519mtrpbf 8 lead mlpd (3 x 3 mm body) 3000 per reel * IR3519mpbf 8 lead mlpd (3 x 3 mm body) 100 piece strips IR3519strpbf 8 lead son 2500 per reel * IR3519spbf 8 lead son 95 per tube * samples only
IR3519 page 2 of 10 www.irf.com 8/15/08 absolute maximum ratings absolute maximum rating s (referenced to gnd) boot voltage: ................................................ 40 v ph voltage: .............. -5v(100ns),-0.3v(dc) to 35 v ugate voltage: ...... -5v(100ns),-0.3v(dc) to 40 v lgate voltage: ......... -5v(100ns),-0.3v(dc) to 8 v boot - ph voltage: ............................ -0.3v to 8 v ugate - ph voltage: .......................... -0.3v to 8 v vdd: .................................................................. 8 v gnd: .................................................. -0.3 v to 0.3v all other pins ........................................ -0.3v to 8 v operating junction temperature .. -10c to +150 o c msl rating .................................................. level 2 reflow temperature ?................................260 o c storage temperature range .......... -65 o c to 150 o c esd rating ......... hbm class 1c jedec standard stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of t he device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. recommended operating conditions 6.5v vdd 7.5v, 0 o c t j 125 o c electrical specifications the electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. c ugate = 3.3nf, c lgate = 6.8nf (unless otherwise specified). parameter test condition min typ max unit gate drivers ugate source resistance boot ? ph = 7v. note 1 1.0 2.5 ? ugate sink resistance boot ? ph = 7v. note 1 1.0 2.5 ? lgate source resistance vdd ?gnd = 7v. note 1 1.0 2.5 ? lgate sink resistance vdd ? gnd = 7v. note 1 0.4 1.0 ? ugate source current boot=7v, ugate=3.5v, sw=0v. note 1 2.0 a ugate sink current boot=7v, ugate=3.5v, sw=0v. note 1 2.0 a lgate source current vdd=7v, lgate=3.5v, gnd=0v. note 1 2.0 a lgate sink current vdd=7v, lgate=3.5v, gnd=0v. note 1 5.0 a ugate rise time boot ? ph = 7v, measure 1v to 4v transition time. 5 ns ugate fall time boot - ph = 7v, measure 4v to 1v transition time. 5 ns lgate rise time vdd ? gnd = 7v, measure 1v to 4v transition time. 10 ns lgate fall time vdd ? gnd = 7v, measure 4v to 1v transition time. 5 ns
IR3519 page 3 of 10 www.irf.com 8/15/08 parameter test condition min typ max unit lgate low to ugate high delay boot = vdd = 7v, ph =0v gnd = 0v, measure time from lgate falling to 1v to ugate rising to 1v. 5 15 ns ugate low to lgate high delay boot = vdd = 7v, ph =0v gnd = 0v, measure time from ugate falling to 1v to lgate rising to 1v. 5 15 ns minimum pulse width note 1 30 50 ns passive gate pull-down resistance 20 k ? ph bias current measure with pwm=tri-state, ph=1v -2 -10 vdd under voltage lockout comparator (v uvlo ) start threshold 5.65 6.0 6.3 v stop threshold 5.4 5.7 6.1 v hysteresis start ? stop 0.4 v pwm input ugate threshold voltage, v ugate th pwm rising 2.0 2.2 2.4 v ugate threshold voltage, v ugate th pwm falling 1.9 2.1 2.3 v ugate threshold hysteresis 30 90 170 mv lgate threshold voltage, v lgate th pwm falling 0.6 0.8 1.0 v lgate threshold voltage, v lgate th pwm rising 0.74 0.9 1.1 v lgate threshold hysteresis 30 90 170 mv tri-state bias voltage, v pwm tri 1.2 1.6 1.8 v input bias current v(pwm) = 0v -260 -210 -160
IR3519 page 4 of 10 www.irf.com 8/15/08 note 1: guaranteed by design, but not tested in production parameter test condition min typ max unit en/uv input/output threshold voltage, v en th en/uv rising, uv fet off 1.1 1.75 2.0 v en/uv falling, uv fet off 0.6 1.1 1.4 v hysteresis 350 650 800 mv pull-down resistance 600 1000 1400 ? sink current vdd = 2.5v, v(en/uv) = 0.6v 200 350 500 bootstrap pfet forward voltage i(boot) = 30ma, vdd = 7v 450 660 750 mv general vdd supply current en = 0, pwm = tri-state 50 100 ua vdd supply current en = 3.3 v, pwm = tri-state 700 1000 ua
IR3519 page 5 of 10 www.irf.com 8/15/08 ic pin order and description name number i/o level description ugate 1 vin + vdd high-side driver output and input to gatel non-overlap comparator boot 2 vin +vdd bootstrapped gate drive supply ? connect a capacitor to phase pwm 3 up to 5v logic input gnd 4 reference ic power return ? connect to source of synchronous mosfet lgate 5 vdd lower gate drive for synchronous mosfet vdd 6 typical 7v ic bias supply en/uv 7 3.3v bias this pin to > 2v to enable and < 0.6v to disable the ic (both gate outputs held low). if vdd is below the under voltage lockout threshold this pin is internally pulled low and provides an input power good indicator function. if the power good and enable functions are not required this pin can be connected to the vdd pin. do not float this pin as incorrect operation could occur. ph 8 vin return for high-side driver, reference for gatel non-overlap comparator, and input to the diode emulation comparator.
IR3519 page 6 of 10 www.irf.com 8/15/08 block diagram
IR3519 page 7 of 10 www.irf.com 8/15/08 functional description IR3519 switches the lgate and ugate signals when vdd is greater than v uvlo and en/uv voltage is greater than v en th . the gate drive logic features adaptive dead time which prevents simultaneous conduction of the upper and lower mosfets. the lower gate voltage must be below approximately 1v after pwm goes high and before the upper mosfet can be gated on. also the upper gate voltage, the different voltage between ugate and ph, must be below approximately 1v after pwm goes low and before the lower mosfet can be gated on. the internal logic will evaluate the pwm voltage level. the pwm is considered high when its level is greater than v ugate th . pwm is considered low when its level is below v lgate th . in the middle voltage region of v ugate th and v lgate th , the pwm will be in tri-state mode. in the absence of external drive, the pwm pin is pulled to this middle region by a v pwm tri source through an internal resistor. after a short time delay in this middle region, IR3519 is forced into a low power state. the ugate logic evaluates its input logic signal and generates a ph referenced to drive the ugate pin, which turns on/off the external high side mosfet. ph pin is to be connected to the source of the upper mosfet, the buck inductor, and to the drain of the lower mosfet. to turn on the upper n channel mosfet, a bootstrap circuit is required. this is accomplished by charging a capacitor (connected boot to ph) after the lower mosfet conducts and the ph pin is substantially at gnd. vdd provides the charging current through an internal bootstrap diode. the minimum boot capacitor value is calculated below. the boot capacitor starts the cycle fully charged to a voltage of v b (0). an equivalent gate drive capacitance is calculated by consulting the high side mosfet data sheet and taking the ratio of total gate charge at the vdd voltage, q g (vdd), to the vdd voltage. q g (vdd)/vdd is the equivalent gate drive capacitance c g which will be used in the following calculations. the voltage of the capacitor pair c b and c g after c g becomes charged at c b ?s expense will be v b (0)- v. choose a sufficiently small v such that v b (0)- v exceeds the maximum gate threshold voltage to turn on the high side mosfet. since total charge q t is conserved, we can write the following equation. ) c (c ) v(t q c (0) v g b on t b b + ? = = ? after rearranging this equation, it becomes the equation below. ? ? ? ? ? ? ? ? ? ? = 1 v (0) v c c b g b choose a boot capacitor value larger than the calculated c b . the voltage rating of this part needs to be larger than v b (0) plus the desired derating voltage. its esr and esl needs to be low in order to allow it to deliver the large current and di/dt?s which drive mosfets most efficiently. in support of these requirements a ceramic capacitor should be chosen. the lgate logic evaluates its input signal and generates a gnd referenced to drive the lgate pin, which turns on/off the external low side mosfet. the lgate logic uses vdd source to turn on the low side mosfet because the source of low side mosfet is reference to gnd. layout recommendation one 1uf high quality ceramic capacitor is required to place near vdd pin as possible. other end of capacitor is recommended to tie to gnd pin plan as close to as ic possible. this gnd island plan can be via or directly connect to the main gnd plan or layer. if the connection of gnd pin to the source of low side mosfet through an internal layer, it is recommended connecting through at least 2 vias by build a small island of next to gnd pin. the boot capacitor needs to place close to boot and ph pins to reduce the impedance during the turn-on process of high side mosfet. the main function of boot capacitor is to supply the energy for turning on high side mosfet. it is recommended to add zero ohm resistor in series with boot capacitor as place holder. when connecting the trace for ugate and lgate signals, one needs to keep in mind that the signal return path is as an important as signal path. the return path contains both ac and dc current. dc current takes the least resistance path. ac current takes the least impedance path. the return path is exits whether or not provide it. if the designer is overlooked the return path, the ac current will cause the more noise in the system. therefore, it is recommended to place lgate signal path on top next to the source of low side mosfet path and place ugate signal path on top of ph signal path. when connecting phase signal path to power stage area, phase signal needs to chose quite area. figure 1 shows the location of connection from power stage to IR3519 phase pin less noise sensitive than figure 2.
IR3519 page 8 of 10 www.irf.com 8/15/08 figure 1: phase node sense with less noise figure 2: phase node sense with more noise ph ph ph ph
IR3519 page 9 of 10 www.irf.com 8/15/08 package information 3 x 3mm mlpd
IR3519 page 10 of 10 www.irf.com 8/15/08 8l son data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 05/07
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